`timescale 1ns / 1ns

module huawei8  //四位超前进位加法器
(
    input  wire [3:0] A,
    input  wire [3:0] B,
    output wire [4:0] OUT
);
    wire [1:0] low_sum;
    wire low_out_c;
    add22 low_add (
        .in_1 (A[1:0]),
        .in_2 (B[1:0]),
        .sum  (low_sum),
        .out_c(low_out_c)
    );

    wire [1:0] high_sum;
    wire high_out_c;
    add22 high_add (
        .in_1 (A[3:2]),
        .in_2 (B[3:2]),
        .sum  (high_sum),
        .out_c(high_out_c)
    );

    wire [1:0] final_sum;
    wire final_out_c;
    wire [1:0] final_in_c;
    assign final_in_c[0] = low_out_c;
    assign final_in_c[1] = 0;
    add22 final_add (
        .in_1 (high_sum),
        .in_2 (final_in_c),
        .sum  (final_sum),
        .out_c(final_out_c)
    );

    assign OUT[1:0] = low_sum;
    assign OUT[3:2] = final_sum;
    assign OUT[4]   = high_out_c | final_out_c;
endmodule

module add11 (
    input  wire in_1,
    input  wire in_2,
    output wire sum,
    output wire out_c
);
    assign sum   = in_1 ^ in_2;
    assign out_c = in_1 & in_2;
endmodule

module add22 (
    input wire [1:0] in_1,
    input wire [1:0] in_2,
    output wire [1:0] sum,
    output wire out_c
);
    wire low_sum;
    wire low_out_c;
    add11 low_add (
        .in_1 (in_1[0]),
        .in_2 (in_2[0]),
        .sum  (low_sum),
        .out_c(low_out_c)
    );

    wire high_sum;
    wire high_out_c;
    add11 high_add (
        .in_1 (in_1[1]),
        .in_2 (in_2[1]),
        .sum  (high_sum),
        .out_c(high_out_c)
    );

    wire final_sum;
    wire final_out_c;
    add11 final_add (
        .in_1 (high_sum),
        .in_2 (low_out_c),
        .sum  (final_sum),
        .out_c(final_out_c)
    );

    assign out_c  = high_out_c | final_out_c;
    assign sum[0] = low_sum;
    assign sum[1] = final_sum;
endmodule
